Embedded vertical dram arrays with silicided bitline and polysilicon interconnect

ABSTRACT

A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M 0  metallization layer.

FIELD OF THE INVENTION

[0001] The present invention relates to a method for fabricatingsemiconductor circuits containing both DRAM and logic cells. Inparticular, the invention relates to fabricating semiconductor circuitscontaining vertical pass gate embedded DRAM (EDRAM) arrays and dualworkfunction logic gates.

BACKGROUND OF THE INVENTION

[0002] With the advent of Large Scale Integration (LSI), many integratedcircuit designs include several circuit functions on a singlesemiconductor substrate, such as memory storage and logic functions foraddressing and accessing the memory. In the case where a logic regionand a DRAM cell (memory) region are formed on the same substrate, thecircuitry is commonly referred to as an embedded DRAM. The integrationof logic and memory regions improves overall device performance bydecreasing communication delays between memory devices on one chip andlogic devices located on a second chip. In addition to the improvementsin device performance, processing costs for integrating memory and logiccircuit functions on the same semiconductor substrate potentially couldbe reduced due to the sharing of specific processing steps used tofabricate both types of devices. Present trends in DRAM technology aredriving towards continued scaling of minimum feature size (F) in theDRAM array, and more compact cell layouts (e.g., 7F², 6F², etc.). As aresult, the above noted problems in the prior art become even moreproblematic, especially for devices where F=100 nm and smaller.

[0003] DRAM circuits will usually include an array of memory cellsinterconnected by rows and columns, which are known as wordlines andbitlines, respectively. Reading data from, or writing data to the memorycells is achieved by activating selected wordlines and bitlines.Typically, the DRAM memory cell comprises a MOSFET (metal oxidesemiconductor field effect transistor) connected to a capacitor. TheMOSFET generally includes a gate region and diffusion regions. Thediffusion regions, depending on the operation of the transistor, areoften referred to as either drain or source regions.

[0004] There are different types of MOSFETs. Trench-gated MOSFETs are aclass of MOSFETs in which the gate is positioned in a trench that isformed at the surface and extends into the silicon. The gate is formedin a lattice-like geometric pattern which defines individual cells ofthe DRAM; the pattern normally taking the form of closed polygons(squares, hexagons, etc.) or a series of interdigitated stripes orrectangles. The current flows in vertical channels which are formedadjacent to the sides of the trenches. The trenches are filled with aconductive gate material, typically doped polysilicon, which isinsulated from the silicon by a dielectric layer normally consisting ofsilicon dioxide.

[0005] The trench-gated MOSFETs are normally formed by etching trenchesof various dimensions into a silicon substrate. The gate trenchesnormally extend into the substrate and are frequently rectangular, withflat bottoms bounded by corners. Trenches commonly contain storagecapacitors below the MOSFETs and have N+ doped polysilicon as one plateof the capacitor (a storage node). The other plate of the capacitor isformed usually by diffusing N+ dopants out from a dopant source into aportion of the substrate surrounding the lower part of the trench.Between these two plates a dielectric layer is placed which therebyforms the capacitor.

[0006] Typically, isolation regions are formed in the substrate toprevent carriers from traveling through the substrate between adjacentdevices. The isolation regions are generally thick field oxide regionsextending below the surface of the semiconductor substrate. One suchtechnique for forming the isolation region is the local oxidation ofsilicon, i.e., LOCOS regions. LOCOS field oxidation regions are formedby first depositing a layer of silicon nitride on the substrate surfaceand then selectively etching a portion of the silicon nitride layer toform a mask exposing the substrate where the field oxidation will beformed. The masked substrate is then placed in an oxidation environmentand a thick layer of oxide is selectively grown in the exposed maskregions forming an oxide layer extending above and below the substratesurface. An preferred alternative to LOCOS field oxidation is theformation of shallow trench isolation regions in contemporary CMOStechnology, commonly referred to by those in the art as an STI region.In the process of forming the STI regions, a deep trench is formed inthe semiconductor substrate by, for example, anisotropic etching. Thetrench is then filled with oxide back to the surface of the substrate toprovide an isolation region between adjacent devices.

[0007] In a typical DRAM array, the wordlines need to be capped with aninsulator to allow formation of borderless diffusion contacts, whereasin the logic supports the gate conductors must be exposed to allow theintroduction of dual workfunction doping and silicidation. Silicidedgates and source/drain regions greatly complicate the processes forforming array MOSFETs since the array MOSFETs need bitline contactswhich are borderless to adjacent wordline conductors. In addition, ithas been found that silicide junctions in the array frequently result inincreased current leakage of the memory device. Conventional solutionsto these integration problems require additional masking steps to removethe insulating gate cap from the support MOSFETs prior to thesilicidation process.

[0008] Problems encountered in the formation of vertical pass gateembedded DRAM (EDRAM) arrays and dual workfunction logic gates includethe lithography steps used to simultaneously form the support gates andwordlines. The wordlines used in the array have tight pitch requirementswhereas the support regions have relatively relaxed pitch features.Lithographic patterning these different pitches typically requirescomplex solutions, such as alternating phase shift masking techniquesand the like, to overcome these difficulties. It is desirable to havethe pitch requirements for the array and supports be similar or morerelaxed to overcome these well known lithographic problems. However,this is not currently feasible as circuitry density increases and assuch, common practice is to separately pattern the array and supports.

[0009] Another problem with prior art processes is in the formation ofthe local interconnects. Conventionally, one of the metallization layersis used for forming both the bitline and the local interconnects. It ispreferred to have a simpler process that eliminates the metallizationlayer and its attendant processing to form the local interconnect andmetal layer. U.S. patent application Ser. No. 09/725,412 to Mandelman etal. filed on Nov. 29, 2000 shows how to form dual work function logicgates with vertical DRAM cells using a raised shallow trench isolation(RSTI) process. This process has the disadvantage that the support logicdevices are subject to the thermal processes of the shallow trenchisolation which can degrade the well profile.

[0010] U.S. patent application Ser. No. 09/706,492 to Mandelman et al.filed on Nov. 3, 2000 overcomes many of the above noted thermalproblems. The process disclosed therein generally includes a) patterningonly the array gate wiring for the vertical transistors; b) formingsilicided bitlines and peripheral transistors concurrently and c)showing a metal to form local interconnects. However, this methodologybecomes difficult to implement for tight array pitches patterned with193 nm lithography.

[0011] Accordingly, there is a need for improved processes that addressthese concerns and provide a process that can be used for the morecompact cell layouts.

BRIEF SUMMARY OF THE INVENTION

[0012] A process and structure for producing high density embedded DRAMand logic structures is described. The process includes fabricatingembedded vertical DRAM arrays with a silicided bitline and a polysiliconinterconnect. In one embodiment, the method of forming a memory arrayand support transistors on a semiconductor substrate comprises providinga substrate including a memory structure having an array region and asupport region separated by an isolation region, wherein the arrayregion includes a plurality of dynamic random access memory cellsembedded in the substrate, wherein adjacent dynamic random access memorycell are connected to each other through bitline diffusion regions, andwherein the memory structure is capped with a top oxide layer; applyinga block mask to protect the array region while stripping the top oxidelayer from the support region; forming support implants, forming asupport gate oxide layer and patterning a first polysilicon layer ontothe support gate oxide layer; forming a tungsten nitride, tantalumnitride or titanium nitride layer on all exposed surfaces of thesubstrate; forming a conductive metal layer on the nitride layer;forming an insulating layer on the conductive metal layer; removingportions of the conductive nitride layer, the conductive metal layer andthe dielectric capping layer from the support region to form a supportgate structure, wherein the support gate structure comprises the gateoxide layer, the first polysilicon layer, the conductive nitride layer,the metal layer and the dielectric capping layer, wherein the supportgate structure further includes forming an insulated spacer on thesidewall of the gate structure and removing the conductive nitridelayer, the conductive layer and the dielectric capping layer structurefrom the isolation region to define a local interconnect region; forminga protective layer on all exposed surfaces of the substrate; forming anarray gate structure in contact with the memory cell and exposing aportion of the bitline by removing portions of the protective layer, theconductive nitride layer, the metal layer and the dielectric cappinglayer from the array region, and simultaneously removing the protectivelayer from the isolation region; forming an spacer layer on sidewalls ofthe array gate structure; depositing a second polysilicon layer onto thesubstrate; selectively patterning and etching the second polysiliconlayer in the isolation region to forma landing pad while removing thepolysilicon layer in the support regions; and simultaneously formingsilicide layers on an exposed portion of the source and drain regions inthe support region, on the second polysilicon layer overlaying thebitline diffusion regions in the array region, and on the secondpolysilicon layer defining the landing pad.

[0013] In another embodiment of the process, the method of forming amemory array and support transistors on a semiconductor substrateincludes providing a memory structure having an array region and asupport region separated by an isolation region, wherein the arrayregion includes a plurality of dynamic random access memory cellsembedded in the substrate, wherein adjacent dynamic random access memorycells are connected to each other through bitline diffusion regionswhich are capped with a top oxide layer; depositing a barrier layer, ametal layer, and a dielectric capping layer onto the substrate; removingportions of the barrier layer, the polysilicon layer, and the dielectriccapping layer from the substrate to form an array gate structure;depositing a layer of nitride onto the substrate and removing thenitride layer from the non-array regions and the top oxide layer in thesupport region; forming a support sacrificial oxide layer, formingsupport implants, removing the sacrificial layer and forming a supportgate oxide layer; depositing a first layer of polysilicon onto thesubstrate and etching the first polysilicon layer to the support gateoxide to form a support gate structure; forming spacers on the sidewallsof the array gate structure and support gate structure, wherein thespacer is removed in array regions for forming a bitline contact;depositing a second polysilicon layer and applying a mask to pattern andform a landing pad in the array and gate conductors for the supporttransistors; siliciding the landing pad, the support gate structure, thesupport gate conductors and the second polysilicon layer overlying thebitline diffusion regions in the array region.

[0014] In another embodiment of the process, a method of forming amemory array and support transistors on a semiconductor substrateincludes forming a trench capacitor in a silicon substrate having a gateoxide layer, a polysilicon layer, and a top cap layer deposited thereon;patterning an array gate structure by removing portions of thepolysilicon layer and the cap layer; depositing a nitride layer onto thesubstrate; applying a patterned mask to selectively etch the nitridelayer in the support region and isolation region, and forming asacrificial oxide layer; forming implants in the support region andsubsequently stripping the sacrificial oxide layer and forming a gateoxide layer; depositing and patterning a second layer of polysilicon inthe support region to the gate oxide layer and the gate cap layerforming the gate stack. and in the array region patterning the secondpolysilicon layer to the nitride layer; depositing a second layer ofnitride onto the substrate and a layer of tetraethylorthosilicatethereon; removing portions of the tetraethylorthosilicate layer in thearray region and in a region where a local interconnect is formed;conformally depositing a third layer of polysilicon onto the substrateand planarizing the third polysilicon layer over the gate stack in thesupport region; patterning the third polysilicon layer to define thelocal interconnect, and in the support region, further removing thenitride layer and simultaneously forming implants therein and doping thegate stack; and siliciding the exposed portions of the polysilicon layerin the array region and the local interconnect.

[0015] A semiconductor device including a dual workfunction supporttransistor and an embedded DRAM array free of a M0 first metal layerincludes a support region comprising a gate structure, a source and adrain region adjacent to the gate structure, and a silicide layerdisposed on the source and drain regions, wherein the gate structurecomprises a dielectric capping layer, a metal conductor and apolysilicon layer; an array region comprising a plurality of embeddedDRAM cells, a bitline diffusion region electrically connecting adjacentDRAM cells, a polysilicon layer and a silicide layer disposed on thepolysilicon layer; an isolation region, wherein the isolation regionelectrically separates the support region from the array region; and aninterconnect structure disposed on the isolation region comprising apolysilicon layer and a silicide layer formed on the polysilicon layer.

[0016] In another embodiment, the semiconductor device structureincludes a support region comprising a gate structure, source and drainregions adjacent to the gate structure, and a silicide layer disposed onthe source and drain regions, wherein the gate structure comprises adielectric capping layer, a metal conductor and a polysilicon layer; anarray region comprising a plurality of embedded DRAM cells, a bitlinediffusion region electrically connecting adjacent DRAM cells, an arraygate stack structure, a polysilicon layer, wherein the polysilicon layerincludes a silicide surface; an isolation region, wherein the isolationregion electrically separates the support region from the array region;and an interconnect structure disposed on the isolation regioncomprising a

[0017] polysilicon layer and a silicide layer formed on the polysiliconlayer.

[0018] In another embodiment, the semiconductor device structureincludes an active wordline comprising a first gate structure formed ona storage capacitor, wherein the first gate structure comprises a metalconductor layer, a dielectric capping layer and a spacer layer formed ona portion of the first gate structure; a passing wordline spaced apartfrom the active wordline, the passing wordline comprising a second gatestructure, wherein the second gate structure comprises a metalconductor, a dielectric capping layer, an underlying oxide layer and aspacer layer formed on a portion of the second gate structure; a bitlinediffusion region separating the active wordline from the passingwordline; and a landing pad comprising polysilicon having a silicidesurface, wherein the landing pad is in contact with the first gatestructure, the second gate structure and the bitline diffusion region.

[0019] In another embodiment, the semiconductor device structureincludes an array region comprising a plurality of embedded DRAM cells,a bitline diffusion region electrically connecting adjacent DRAM cells,an array gate stack structure overlaying each DRAM cell, and a silicidepolysilicon layer, wherein the gate structure comprises a metalconductor layer and a dielectric capping layer and wherein the silicidepolysilicon layer is in contact with the bitline diffusion region andthe dielectric capping layer; a support region comprising a polysilicongate structure, a source and a drain region adjacent to the gatestructure, and a silicide layer disposed on the gate structure and thesource and drain regions; and an interconnect structure overlaying anisolation region, separating the support region from the array region,wherein the isolation region include a silicide polysilicon layer.

[0020] Advantageously, the process and structure eliminates the need fora M0 first metallization layer for sub-8F² cells.

[0021] Other embodiments of the invention are contemplated to provideparticular features and structural variants of the basic elements. Thespecific embodiments referred to as well as possible variations and thevarious features and advantages of the invention will become betterunderstood when considered in connection with the accompanying drawingsand detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIGS. 1-5 show schematic cross-sectional views illustratingfabrication of a DRAM array and supports constructed in accordance withan embodiment of the present invention.

[0023]FIGS. 6A and 6B show schematic top down and cross-sectional viewsillustrating fabrication of a DRAM array and supports constructed inaccordance with an embodiment of the present invention.

[0024]FIG. 7A and 7B show schematic top down and cross-sectional viewsdepicting a landing pad between adjacent wordlines.

[0025] FIGS. 8-10 show schematic cross-sectional views illustratingfabrication of a DRAM array and supports constructed in accordance withan embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0026] The present invention is directed to a process for fabricating avertical embedded DRAM array and dual workfunction support devices on asemiconductor substrate. The process, in accordance with the presentinvention, advantageously eliminates numerous processing steps relativeto conventional fabrication. A metallization layer is commonly used forforming both the bitline and the local interconnects. This metal layeris commonly referred to as the M0 layer. In the present process, thelocal interconnects and bitlines are both silicided, thereby eliminatingthe need for the M0 metal layer as well as numerous process stepstypically required to form the metal layer. Moreover, the silicidationof the bitlines (especially advantageous for sub 8F² cells) relaxes thepitch requirement needed to form the first metal layer since the M0metal layer generally has the tightest pitch requirements and presentsthe greatest photolithographic challenges. The use of relaxed pitchesfor the metal layers advantageously minimizes the well knowndifficulties associated with conventional lithographic patterning ofdense (memory type) and isolated (logic type) features within the samelayer. As a result, proximity effects during lithographic processing areminimized. Consequently, reliance on complicated optical proximitycorrection schemes, alternating phase shift masking techniques and thelike is reduced significantly since formation of the first metal layer(i.e., M0 layer) is no longer required.

[0027] FIGS. 1-5 are schematic, cross-sectional diagrams used to depictsteps in an embodiment for fabricating a vertical embedded DRAM andlogic support on the same substrate.

[0028] Turning now to FIGS. 1, the illustrated integrated circuit,generally designated as reference number 200, is a suitable substratefor practicing the present invention. The integrated circuit includes amemory circuit region 204 and a logic circuit region 206 on asemiconductor substrate 202, wherein the memory circuit region 204 andthe logic circuit region 206 are separated by an isolation region 208.Although the drawings depict the isolation region as a shallow trenchisolation (STI) region, the invention is not to be construed as beinglimited to STI regions. Suitable semiconductor substrates include, butare not limited to, Si, SiGe, Si/SiGe, silicon-on-insulators (SOI) andthe like.

[0029] It is noted that the drawings illustrate only one of each region204 and 206 in the structure. In practice, depending on the design, thesubstrate may include numerous memory and support regions. Standardprocessing known in the art for fabricating vertical MOSFET DRAMs in thesubstrate 202 is applied through the step of defining an active area andafter shallow trench isolation planarization. These standard processingtechniques include formation of the storage capacitors in deep trenches,depositing a top oxide layer (TTO) 210, forming array well implants,forming an implant for bitline diffusion region 214 for connectingadjacent vertical DRAMs, removing the original pad structure, andgrowing a vertical gate oxide layer and a gate conductor layers 220. Thearray gate polysilicon layer 220 is separated from an underlying deeptrench polysilicon region 230 by a trench top oxide layer 226. Thebitline diffusion region 214 is formed in the substrate 202 betweenadjacent vertical DRAM cells and serves to electrically connect thebitline contact of the DRAM cells shown in FIG. 1. Also included are acollar region 222 and a buried strap 224.

[0030] The present invention is not limited to the exact memorystructure shown in the figures. The DRAM cells may also include a buriedexterior counter-electrode about the trench, or a counter-electrodeformed inside the trench and a node dielectric formed on thecounter-electrode. Deep trench polysilicon is formed on the nodedielectric. Other memory structures which include the basic elementsshown, but having different configurations are also contemplated herein.FIG. 1 shows the structure of a particular sub-8F² cell, but theinvention may be modified for other sub-8F² cells or for an 8F² verticalpass gate DRAM cell as will be discussed in further detail below.

[0031] A block mask is used to selectively etch the TTO layer 210 fromthe support region 206 and polysilicon 221 is then deposited therein(after the support implants and support gate oxidation). The gate oxidelayer is formed by recognized procedures and is shown as referencenumeral 240. The polysilicon layer 221 is subsequently etched using amask from the array region 204. The thickness of the top oxide layer 210and polysilicon 221 are approximately the same.

[0032] The dual workfunction implants may be performed at this time inthe support polysilicon using conventional photolithographic processing.Depending on the particular desired circuitry, the gates in the supportregion can be defined as either a P channel (PFET device) or as an Nchannel (NFET device). In the case of PFET devices, selectiveimplantation of boron dopant ions is preferably performed in thepolysilicon 221 of the support regions, whereas in NFET devices,selective implantation of arsenic or phosphorous ions is preferablyemployed. The energies, doses and selective processing required for eachchannel type are conventional and well within the skill of those in theart. The ion implantation of NFET supports may also be used for dopingthe polysilicon gates in the DRAM region. In contrast, during definitionof the PFET logic gate structures, the DRAM region is protected by alayer of photoresist. Residual photoresist after processing each type ofchannel is removed with conventional plasma ashing and subsequent wetcleans as is known to those skilled in the art. A rapid thermal anneal(RTA) procedure can then be used to activate all of the doped regions oralternatively, the RTA procedure can be performed during subsequentprocessing of the integrated circuit.

[0033]FIG. 2 illustrates the memory structure after various layers havebeen formed in the support and array regions. The support polysilicon221 is separated from the underlying surface by the gate oxide layer240. A barrier layer 250 is deposited onto the array and supportsurfaces using conventional deposition processes such as chemical vapordeposition (CVD), plasma assisted CVD, sputtering and the like.Preferably, the barrier layer is formed from a metallic nitridecomposition. Nitrides suitable for use in the present invention include,but are not limited to titanium nitride, tantalum nitride, tungstennitride and the like. Other materials suitable for use as barrier layerswill be apparent to those skilled in the art in view of this disclosure.The thickness of the barrier layer may vary and is not critical to thepresent invention. Optionally, a thin silicon layer may be sputtered (ordeposited) to help with adhesion of the barrier layer to the top oxidelayer 210 in the array.

[0034] A metal conductor layer 252, preferably a tungsten silicide(WSi_(x))/tungsten (W) layer, is next deposited utilizing one of theconventional deposition processes described above. The metal conductorlayer 252 is used to form the wordline stack in the array region. Itshould be noted that the process is not limited to this particularwordline structure. The thickness of the conductor may vary depending onthe deposition process. The metal conductor 252 is capped with a thicklayer of dielectric material 254, such as tetraethylorthosilicate (TEOS)or silicon nitride or TEOS with a thin layer of silicon nitride (SiN) ontop (not shown). The deposited dielectric layer 254 forms an insulatingcap over the wordline conductors. Preferably, the dielectric material254 is a TEOS layer with a thin layer of about 10-30 nm of SiN on itsupper surface. Then, using conventional lithography and etchingprocesses, the gate stacks in the support region 206 are patterned asshown in FIGS. 3 and 4.

[0035] At the time of patterning the array wordlines, the stackthickness in both the array and support regions are approximatelycoplanar. The support logic gates are first patterned and etched to thegate oxide layer 240 using conventional processes. At this point, gatesidewall oxidation layers 256 are grown on the sidewalls of the gatestacks, followed by deposition of a thin dielectric layer 258 onto thesubstrate. Preferably, the dielectric layer is silicon nitride at athickness of about 10 nm. The support extension implants 257 areperformed and an insulating layer 260 of TEOS is deposited onto thesubstrate.

[0036] FIGS. 4-5 illustrate the memory and support regions afterdefining the memory and support stacks. The array wordlines arepatterned and etched. The support regions are protected by oxide layer260. A resist mask is then applied and exposed in the array and inregions where a local interconnect 306 is to be formed. The top oxidelayer 210 is removed in the array region selective to the top of thedielectric layer 254. The oxide and dielectric layers 260 and 258respectively, are also removed in regions where the local interconnect306 is to be formed. For example, portions of the top oxide layer 210(as shown in FIG. 3) are removed over the bitline diffusion regions 214in the array region 204. In addition, the dielectric layer 258 isselectively removed to expose the (n⁺) interconnect regions as shown inFIG. 4. Silicon nitride spacers 270 are then formed on the sidewalls ofthe memory stacks in the array region. A second layer of n+ dopedpolysilicon 300 is conformally deposited over the substrate andplanarized to a level above the gate stack. Polishing may be used toplanarize the doped polysilicon surface and is accomplished byconventional chemical mechanical polishing techniques known to thoseskilled in the art.

[0037] A hardmask, such as boron silicate glass (BSG) phosphoroussilicate glass (PSG), arsenic silicate glass (ASG) or the like may thenbe applied and the second layer of polysilicon 300 is patterned with aphotoresist mask and selectively etched to the STI oxide 260 in thearray, selectively etched to the dielectric layer in the interconnectregion, and completely removed from the support regions. If a hardmaskis utilized, it is then stripped selective to the substrate. If needed,an additional oxide layer, such as TEOS, is then deposited and spacers360 etched. These additional spacers form on the sides of the bitlineand local interconnect. The nitride 258 is then etched. The deep n+ andp+ implants 357 are performed while masking the PFETs and NFETsrespectively. The outdiffused n-type dopant forms n+ junctions 267 inregions of the local interconnects.

[0038] Silicide regions 309 are then formed on surfaces of the exposedpolysilicon 300. Specifically, the silicide regions are formed on thearray bitline diffusion region, the interconnects and the supportsource/drain region. A rapid thermal anneal procedure or the like isused to form the silicide regions. FIG. 5 illustrates the resultingstructure with the silcided regions 309. It should be noted thatselective silicidation of the polysilicon layer 300 and the supportsource/drain regions eliminates the need for an M0 metal layer forsub-8F²cells FIG. 5 is intentionally showing a different interconnect aswould be expected from FIG. 4 to show the different structures possible.FIG. 5 shows silicided junctions and a silicided interconnect separatefrom the junctions.

[0039] Standard processing then continues to form the various wiringlevels, vias and interlevel dielectric layers. For example, aninterlevel dielectric layer may be deposited on the structure, patternedand etched to form vias or the like in the interlevel dielectric layer.

[0040] In another embodiment, preferably used for the fabrication of 8F²vertical DRAM cells, the SiN spacer 270 is selectively etched in regionswhere the bitline contact is to be made in the manner shown in the topdown view of FIG. 6A and corresponding cross-sectional view shown inFIG. 6B. In this process, the spacer 270 is not etched in the sameactive array regions (AA^(n)) between adjacent wordlines (WL^(n)) wherethe bitlines are not contacted. The hatched regions show the regionswhere the SiN spacer 270 is etched. This allows the bitline diffusion214 to be exposed only in the hatched region. It is important to notethat the wordline is isolated from the substrate by the top oxide 210and is shorted by the bitline diffusion region 214. The depositedpolysilicon layer 300 is then patterned as a landing pad resulting inthe structure shown in FIGS. 7A and 7B. The landing pads are patternedas shown in FIG. 7 by the hatched region. Optionally, the polysiliconlayer 300 may require a CMP planarization and subsequent hardmask asdiscussed in the previous embodiment. These polysilicon landing pads arethen silicided and electrically connected with a subsequent metal wiringlevel by means of a metal contact. In this embodiment, the metal wiringlevel serves as the bitline.

[0041] In another embodiment, a barrier layer 250, a conductor 252 and adielectric layer 254 are deposited onto the structure as shown inFIG. 1. As previously described, the dielectric layer 254 is preferablya combination of TEOS and a thin layer of silicon nitride. The arraygate is patterned and etched to the TTO layer 210. A silicon nitridelayer 301 is then deposited. A mask is used to selectively etch thesilicon nitride layer 301 in the non-array portions 206 of the wafer.The TTO layer 210 is then removed in the non-array portions and asupport sacrificial oxide layer (not shown) is thermally grown. Duringthese process steps, the array regions 204 are protected by the siliconnitride layer 301. The support implants (wells and threshold adjust) areperformed, the sacrificial oxide layer is stripped and the support gateoxide layer 303 is grown as shown in FIGS. 8 and 9.

[0042] Turning now to FIG. 10, a layer of intrinsic polysilicon 302 isdeposited onto the substrate and patterned with the support gateconductor mask. Optionally, a hard mask may be used for this part of theprocess. The polysilicon layer 302 is then etched to the gate oxide 303in the support regions 206 and completely cleared selective to the gatecap 254 and silicon nitride layer 301 in the array region. The supportextension and halo implants are performed after an optional sidewalloxidation. The PFET implants may be performed after an optional SiNspacer layer is formed (not shown). A barrier nitride layer 258 is thendeposited onto the substrate as shown in FIG. 9. Subsequently, a TEOSliner layer 260 is then deposited onto the substrate and removed in thearray and in the regions where the local interconnect is to be formed.The TEOS liner is removed by using a photoresist mask and conventionalwet etching processes. Then, the SIN layer is removed by exposing thelayer to RIE and etching the TTO 210 in the array with a RIE selectiveto the silicon 202 underlying the array region and the interconnectregion. The resist used for the mask is then selectively stripped fromthe substrate surface.

[0043] The etching of the nitride layers 301 and 258 forms the spacer270 in the array regions. A layer of n+ doped polysilicon 300 isconformally deposited and planarized over the gate stack. An optionalBSG hardmask (used for planarization reasons) is used to pattern the n+doped polysilicon (with a photoresist mask) and the bitlines and localinterconnects are defined. Once the BSG is stripped, an additional TEOSlayer may be deposited and spacers 360 etched. The nitride in thesupport gate regions are then etched, the n+ and p+ implants areperformed which also dopes the gate stack 302. The gate stack 302, then+ interconnect and the n+ poly bitline are then silicided. The completestructure is shown in FIG. 10. The rest of the process followsconventional process steps as is recognized by those skilled in the art.

[0044] According to the foregoing, the advantages of the inventioninclude at least the following:

[0045] 1. Separate lithography requirements for the array regionadvantageously results in a more robust photolithography process window.Those skilled in the art will appreciate the difficulties encountered inphotolithographic patterning of memory features and logic supportfeatures within the same layer and the resulting advantages byseparately patterning the significantly different pitch requirements forthe memory and logic regions.

[0046] 2. A conventional first metal layer, commonly referred to as theM0 layer, is not required for sub-8F² cells since the bitlines and localinterconnects are formed by the salicidation of polysilicon. Eliminationof the M0 layer removes the most difficult layer tophotolithographically pattern. The M0 layer typically includes featuresof the smallest dimensions.

[0047] Many modifications and variations of the invention will beapparent to those skilled in the art in light of the foregoingdisclosure. Therefore, it is to be understood that, within the scope ofthe appended claims, the invention can be practiced otherwise than hasbeen specifically shown and described.

What is claimed is:
 1. A method of forming a memory array and supporttransistors on a semiconductor substrate, the method comprising:providing a memory structure having an array region and a support regionseparated by an isolation region, wherein the array region includes aplurality of dynamic random access memory cells embedded in thesubstrate, wherein adjacent dynamic random access memory cells areconnected to each other through bitline diffusion regions, wherein thememory structure is capped with a top oxide layer; applying a block maskto protect the array region while stripping the top oxide layer from thesupport region; forming support implants, forming a support gate oxidelayer and patterning a first polysilicon layer onto the support gateoxide layer; forming a conductive nitride barrier layer, a metal layerand a dielectric capping layer on all exposed surfaces of the substrate;removing portions of the nitride barrier layer, the metal layer and thedielectric capping layer from the support region to form a support gatestructure and removing the nitride barrier layer, the metal layer andthe dielectric capping layer from the isolation region, wherein thesupport gate structure comprises the gate oxide layer, the firstpolysilicon layer, the nitride barrier layer, the metal layer and thedielectric capping layer; forming an insulated spacer on sidewalls ofthe gate structure; forming a protective layer on all exposed surfacesof the substrate; forming an array gate structure in contact with thememory cell and exposing a portion of the bitline diffusion region byremoving portions of the protective layer, the nitride barrier layer,the metal layer and the dielectric capping layer from the array region,wherein the array gate structure comprises the oxide layer, the nitridebarrier layer, the metal layer and the dielectric capping layer, andsimultaneously removing the protective layer from the isolation region;forming a spacer layer on sidewalls of the array gate structure;depositing a second polysilicon layer onto the substrate; selectivelypatterning and etching the second polysilicon layer in the isolationregion to form a landing pad while removing the polysilicon layer fromthe support regions; and simultaneously forming silicide layers on anexposed portion of the source and drain regions in the support region,on the second polysilicon layer overlaying the bitline diffusion regionsin the array region, and on the second polysilicon layer defining thelanding pad.
 2. The method according to claim 1, wherein the oxide layeris tetraethylorthosilicate.
 3. The method according to claim 1, whereinpatterning the second polysilicon layer comprises applying a hardmask ofa glass material and selectively etching to the oxide layer and thedielectric layer in the isolation region.
 4. The method according toclaim 3, wherein the glass material is selected from the group selectedfrom boron silicate glass and phosphorous silicate.
 5. The methodaccording to claim 1, wherein the protective layer comprises a layer ofsilicon nitride overlaying a layer of tetraethylorthosilicate.
 6. Themethod according to claim 1, further comprising forming an interleveldielectric layer on the substrate and providing via openings in theinterlevel dielectric layer exposing the source and drain regions. 7.The method according to claim 1, wherein the isolation region comprisesa shallow trench isolation region.
 8. The method according to claim 1,wherein the nitride layer is selected from the group comprising tungstennitride, tantalum nitride and titanium nitride.
 9. A method of forming amemory array and support transistors on a semiconductor substrate, themethod comprising: providing a memory structure having an array regionand a support region separated by an isolation region, wherein the arrayregion includes a plurality of dynamic random access memory cellsembedded in the substrate, wherein adjacent dynamic random access memorycells are connected to-each other through bitline diffusion regionswhich are capped with a top oxide layer; depositing a barrier layer, ametal layer, and a dielectric capping layer onto the substrate; removingportions of the barrier layer, the polysilicon layer, and the dielectriccapping layer from the substrate to form an array gate structure;depositing a layer of nitride onto the substrate and removing thenitride layer from the non-array regions and the top oxide layer in thesupport region; forming a support sacrificial oxide layer, formingsupport implants, removing the sacrificial layer and forming a supportgate oxide layer; depositing a first layer of polysilicon onto thesubstrate and etching the first polysilicon layer to the support gateoxide to form a support gate structure; forming spacers on the sidewallsof the array gate structure and support gate structure, wherein thespacer is removed in array regions for forming a bitline contact;depositing a second polysilicon layer and applying a mask to pattern andform a landing pad in the array and gate conductors for the supporttransistors; siliciding the landing pad, the support gate structure, thesupport gate conductors and the second polysilicon layer overlying thebitline diffusion regions in the array region.
 10. The method accordingto claim 9, further comprising applying an interlevel oxide layer andthen opening vias in the interlevel oxide layer for forming conductivewiring channels.
 11. The method according to claim 9, wherein thedielectric capping layer comprises a tetraethylorthosilicate layer andsilicon nitride layer.
 12. The method according to claim 9, wherein theisolation region comprises a shallow trench isolation region.
 13. Themethod according to claim 9, wherein the support gate oxide is thermallygrown.
 14. The method according to claim 9, wherein each of the DRAMcells includes a collar oxide region and a buried strap outdiffusionregion.
 15. A method of forming a memory array and support transistorson a semiconductor substrate, the method comprising: forming a trenchcapacitor in a silicon substrate having a gate oxide layer, apolysilicon layer, and a dielectric capping layer deposited thereon;patterning an array gate by removing portions of the polysilicon layerand the cap layer; depositing a nitride layer onto the substrate;applying a patterned mask to selectively etch the nitride layer in thesupport region and isolation region, and forming a sacrificial oxidelayer; forming implants in the support region and subsequently strippingthe sacrificial oxide layer and forming a gate oxide layer; depositingand patterning a second layer of polysilicon in the support region tothe gate oxide layer and the gate cap layer forming the gate stack, andin the array region patterning the second polysilicon layer to thenitride layer; depositing a second layer of nitride onto the substrateand a layer of tetraethylorthosilicate thereon; removing portions of thetetraethylorthosilicate layer in the array region and in a region wherea local interconnect is formed; conformally depositing a third layer ofpolysilicon onto the substrate and planarizing the third polysiliconlayer over the gate stack in the support region; patterning the thirdpolysilicon layer to define the local interconnect, and in the supportregion, further removing the nitride layer and simultaneously formingimplants therein and doping the gate stack; and siliciding the exposedportions of the polysilicon layer in the array region and the localinterconnect.
 16. The method according to claim 15, further comprisingapplying an interlevel oxide layer and then opening vias in theinterlevel oxide layer for forming conductive wiring channels.
 17. Themethod according to claim 15, wherein the dielectric capping layercomprises a tetraethylorthosilicate layer and silicon nitride layer. 18.The method according to claim 15, wherein the isolation region comprisesa shallow trench isolation region.
 19. The method according to claim 15,wherein the support gate oxide is thermally grown.
 20. The methodaccording to claim 15, wherein each of the DRAM cells includes a collaroxide region and a buried strap outdiffusion region.
 21. A semiconductordevice including a dual workfunction support transistor and an embeddedDRAM array free of a M0 first metal layer, the semiconductor devicecomprising: a support region comprising a gate structure, source anddrain regions adjacent to the gate structure, and a silicide layerdisposed on the source and drain regions, wherein the gate structurecomprises a dielectric capping layer, a metal conductor and apolysilicon layer; an array region comprising a plurality of embeddedDRAM cells, a bitline diffusion region electrically connecting adjacentDRAM cells, an array gate stack structure, a polysilicon layer, whereinthe polysilicon layer includes a suicide surface; an isolation region,wherein the isolation region electrically separates the support regionfrom the array region; and an interconnect structure disposed on theisolation region comprising a polysilicon layer and a silicide layerformed on the polysilicon layer.
 22. The semiconductor device accordingto claim 21, wherein the isolation region comprises a shallow trenchisolation region.
 23. The semiconductor device according to claim 21,wherein the array gate stack comprises a metallic conductor and adielectric capping layer.
 24. The semiconductor device according toclaim 21, wherein the dielectric capping layer comprises a layer oftetraethylorthosilicate and a layer of silicon nitride disposed thereon.25. A semiconductor device including a dual workfunction supporttransistor and an embedded DRAM array free of a M0 first metal layer,the semiconductor device comprising: an active wordline comprising afirst gate structure formed on a storage capacitor, wherein the firstgate structure comprises a metal conductor layer, a dielectric cappinglayer and a spacer layer formed on a portion of the first gatestructure; a passing wordline spaced apart from the active wordline, thepassing wordline comprising a second gate structure, wherein the secondgate structure comprises a metal conductor, a dielectric capping layer,an underlying oxide layer and a spacer layer formed on a portion of thesecond gate structure; a bitline diffusion region separating the activewordline from the passing wordline; and a landing pad comprisingpolysilicon having a silicide surface, wherein the landing pad is incontact with the first gate structure, the second gate structure and thebitline diffusion region.
 26. The semiconductor device according toclaim 25, wherein the active wordline overlays an embedded DRAM cell.27. The semiconductor device according to claim 25, wherein the portionof the spacer layer is selectively removed in regions where a bitlinecontact is to be formed.
 28. A semiconductor device including a dualworkfunction support transistor and an embedded DRAM array free of a M0first metal layer, the semiconductor device comprising: an array regioncomprising a plurality of embedded DRAM cells, a bitline diffusionregion electrically connecting adjacent DRAM cells, an array gate stackstructure overlaying each DRAM cell, and a silicide polysilicon layer,wherein the gate structure comprises a metal conductor layer and adielectric capping layer and wherein the silicide polysilicon layer isin contact with the bitline diffusion region and the dielectric cappinglayer; a support region comprising a polysilicon gate structure, asource and a drain region adjacent to the gate structure, and a silicidelayer disposed on the gate structure and the source and drain regions;and an interconnect structure overlaying an isolation region, separatingthe support region from the array region, wherein the isolation regioninclude a silicide polysilicon layer.
 29. The semiconductor deviceaccording to claim 28, wherein the isolation region comprises a shallowtrench isolation region.
 30. The semiconductor device according to claim28, wherein the isolation region comprises a local oxidation of asilicon surface.
 31. The semiconductor device according to claim 28,wherein the dielectric capping layer comprises a layer oftetraethylorthosilicate and a layer of silicon nitride.